Abstract—As multi-core architectures scale in size, on-chip networks (NoC) have become the main communication architecture, replacing dedicated interconnections and shared buses. NoC architectures have to deliver good latency-throughput performance in the face of very tight power and area budgets. Live power measurement is necessary for both hardware and software designer, but it requires too much time for simulation, especially for embedded systems. The major contribution of this paper is to present a simple method for rapidly estimating power consumption and find the hotspots in the network-on-chip(NoC) at two different resolutions. In addition to the low-level cycle-accurate simulation, we also build a high-level NoC simulation platform for multi-core SoCs, called TLM-PVT level. The platform, implemented by SystemC, allows early exploration of the performance and power consumption of NoC, which is able to handle arbitrary topologies and routing schemes. In the experiments, we compare the implemented high-level simulation platform with cycle-accurate simulator. The results show that the TLM-PVT simulator gives a high simulation speedup factor with a negligible performance estimation error margin.
Index Terms—Multi-Core SoC; Network-on-Chip; Low-Power Design; Simulation
Kuei-Chung Chang is with the Department of Information Science and Computer Engineering, Feng Chia University, Taichung, Taiwan. (e-mail:email@example.com).
Chien-Hao Chen, was with the Department of Information Science and Computer Engineering, Feng Chia University, Taichung, Taiwan.
Cite: Kuei-Chung Chang and Chien-Hao Chen, "Multi-Level Simulation Platform of Network-on-Chip for Design Space Exploration," International Journal of Machine Learning and Computing vol. 1, no. 5, pp.504-509 , 2011.