Abstract—Spiking Neural Networks (SNNs) are known as a
branch of neuromorphic computing and are currently used in
neuroscience applications to understand and model the
biological brain. SNNs could also potentially be used in many
other application domains such as classification, pattern
recognition, and autonomous control. This work presents a
highly-scalable hardware platform called POETS, and uses it
to implement SNN on a very large number of parallel and
reconfigurable FPGA-based processors. The current system
consists of 48 FPGAs, providing 3072 processing cores and
49152 threads. We use this hardware to implement up to four
million neurons with one thousand synapses. Comparison to
other similar platforms shows that the current POETS system
is twenty times faster than the Brian simulator, and at least two
times faster than SpiNNaker.
Index Terms—Parallel distributed system, reconfigurable architecture, spiking neural networks.
M. Shahsavari, J. Beaumont and D. Thomas are with the Department of Electrical and Electronic Engineering, Imperial College London, UK (Corresponding author: M. Shahsavari; e-mail: firstname.lastname@example.org).
A. D. Brown is with School of Electronics and Computer Science, University of Southampton, UK.
Cite: Mahyar Shahsavari, Jonathan Beaumont, David Thomas, and Andrew D. Brown, "POETS: A Parallel Cluster Architecture for Spiking Neural Network," International Journal of Machine Learning and Computing vol. 11, no. 4, pp. 281-285, 2021.Copyright © 2021 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).